1. Field of the Invention
The present invention relates to a frame synchronizing apparatus, and more particularly, to a frame synchronizing circuit for performing a frame synchronization of HDTV (high-definition television) digital signals which are transmitted in accordance with a 1125/60 HDTV system studio digital video signal standard which is prescribed by SMPTE 260M.
2. Description of the Related Art
Recently, HDTV devices have been intensively developed for the coming HDTV era. In SMPTE (Society of Motion Picture and Television Engineers), 1125/60 HDTV system studio digital video signal standard which is standardized as SMPTE 260M was developed as a standard for an interface between video devices which are used for producing a program in a studio and have digital video inputs and outputs, among HDTV devices having 1125 horizontal scanning lines and a field frequency of 60 Hz.
In the SMPTE 260M standard, in order to clearly define the timing relationship between the video signal and an analog synchronizing waveform, SAV (Start of Active Video) is transmitted at the start of each video data block, and EAV (End of Active Video) is transmitted at the end of each video data block. By detecting SAV and/or EAV in the transmitted digital signals, each video device can detect the timing of frame synchronization of video signals. Herein, "one frame" corresponds to one horizontal line of analog HDTV signals. FIG. 16 shows the timing relationship between an analog blanking interval, and EAV and SAV.
Table 1 shows the word construction of EAV and SAV.
TABLE 1 ______________________________________ BIT No. 9 8 7 6 5 4 3 2 1 0 WORD No. (MSB) (LSB) ______________________________________ 1 1 1 1 1 1 1 1 1 1 1 2 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 4 1 F V H P.sub.3 P.sub.2 P.sub.1 P.sub.0 0 0 ______________________________________ F = 0 : in a first field period 1 : in a second field period V = 1 : in a field blanking interval 0 : in a period other than the field blanking interval H = 0 : in SAV 1 : in EAV
As is seen from Table 1, in the row of the first word, all of the bits (10 bits) are 1. In the rows of the second and third words, all of the bits are 0. Protection bits P.sub.0, P.sub.1, P.sub.2, and P.sub.3 in the row of the fourth word are used for performing a 1-bit error correction and a 2-bit error detection for the F, V, and H bits in the row of the fourth word.
In cases where the signal transmission between the video devices is performed serially by using one optical fiber and one coaxial cable, as is shown in FIG. 17A, a time division multiplex (TDM) is first performed in the order of Pb/Pr signals and Y signals, and then the transmission is sequentially performed from the LSB (Least Significant Bit). Also, in cases where signals in the RGB system are transmitted after a TDM, as is shown in FIG. 17B, the TDM is performed in the order of G signals, B signals and R signals, and then the transmission is sequentially performed from the LSB.
When the frame synchronization is to be detected from the serially transmitted signals, the frame synchronization can directly be detected from the transmitted serial data. However, the frame synchronization is usually detected after the transmitted serial data is converted into parallel data for the following reasons.
For example, if SMPTE 260M signals are serially transmitted, the transmission is performed at a high rate such as 1.5 Gbps or 2.2 Gbps. In order to detect the frame synchronization from the signals in the form of serial data, it is necessary to provide a detecting circuit which operates at a clock frequency of 1.5 GHz. Such a circuit which operates at such a high rate such as 1.5 Gbps consumes a very large amount of power, which causes the cost to increase. Accordingly, the detection of the frame synchronization after the signal transmission at a high rate is usually performed using parallel data which is obtained by a serial-parallel conversion. When the synchronization detection is performed by using the data after the serial-parallel conversion, a word synchronization can be realized at the same time as the detection of the frame synchronization. That is, the detection of the frame synchronization after the serial-parallel conversion has an additional advantage in that an accurate serial-parallel conversion can be attained at the same time as the detection of the frame synchronization.
In some cases where the frame synchronization can not be detected by using the data after the serial-parallel conversion, there is a possibility that a bit-shift error occurs in the previous serial-parallel conversion.
FIG. 18 shows the configuration of a conventional frame synchronizing apparatus in the RGB system. The transmitted serial data is input into a serial data input terminal 301 of a serial-parallel converting circuit 302 where the serial data is converted into parallel data. The parallel data is fed to a synchronization detecting circuit 303. The parallel data in the RGB system is constituted of 30 bits, i.e., 10 bits (one word) for each of R, G, and B signals.
FIG. 19 shows an example of the synchronization detecting circuit 303. As is seen from FIG. 19, the parallel data of 30 bits is input from an input terminal 41 as one unit. It is determined that there is synchronization by detecting that the succeeding 30 bits of 1, the next succeeding 30 bits of 0, and the next succeeding 30 bits of 0, and then detecting three bits of 1. The three bits of 1 correspond to the H bit (the sixth bit) in the row of the fourth word of EAV shown in Table 1. That is, in the illustrated circuit shown in FIG. 18, the frame synchronization is detected by using EAV.
A bit-shift signal generating circuit 304 generates a 1-bit shift signal when the frame synchronization cannot be detected during several frames. When the serial-parallel converting circuit 302 receives the 1-bit shift signal, the serial-parallel converting circuit 302 shifts the serial-parallel conversion by 1 bit. In other words, the breakpoint for every 30 bits is shifted by 1 bit. After the 1-bit shift signal is generated, the detection of frame synchronization is performed for the succeeding several frames. If the frame synchronization cannot be detected even after the 1-bit shift operation, the operation by the bit-shift signal generating circuit 304 is performed again, so as to detect the frame synchronization. In this way, the 1-bit shift operation is repeatedly performed until the synchronization is detected, so that the frame synchronization is realized. Such a frame synchronization detecting apparatus is described in, for example, Japanese Laid-Open Patent Publication No. 4-119738.
As described above, in The RGB system using SMPTE 260M signals, the serial signals are converted into parallel signals of 30 bits. This means that the bit-shift error occurs at any one of the possible 29 points. It is assumed that there occurs a 29-bit shift error. In such a case, it takes time for 29 frames to detect the synchronization, even if the 1-bit shift is performed once for each frame.
Other than the method in which 1-bit shift is performed as is shown in FIG. 19, a conventional frame synchronizing apparatus can adopt a method in which, in order to shorten the time required for the frame synchronization, a pattern of bit-shift error is read, and a plurality of bits are shifted in one bit-shift operation. In such a case, in order to accommodate any possible bit-shift error patterns, the frame synchronizing detecting circuit necessitates detecting circuits of which the number is equal to the number of bit-shift error patterns.
FIG. 20 shows an example of a frame synchronizing apparatus in the RGB system for correcting the bit-shift error in one shift operation by providing pattern detecting circuits of which the number is equal to the number of bit-shift error patterns. For example, FIG. 21 shows a 2-bit shift error pattern in the case where the 2-bit shift error occurs in the parallel-serial converting circuit. The bit-shift error pattern in FIG. 21 is detected by an RGB 2-bit shift error pattern detecting circuit 502 in FIG. 20.
FIG. 22 shows an exemplary configuration of the 2-bit shift error pattern detecting circuit 502 in FIG. 20. As is seen from FIG. 22, the 2-bit shift error pattern detecting circuit 502 has a relatively large scale circuit which requires at least three AND gates of 30 bits. Each Of the other bit-shift error pattern detecting circuits has the same configuration as that shown in FIG. 22. The conventional frame synchronizing circuit in FIG. 20 requires at least twenty-nine bit-shift error pattern detecting circuits such as that in FIG. 22. Such a number of bit-shift error pattern detecting circuits increase the scale of the conventional frame synchronizing circuit in FIG. 20.
As described above, in the case where the frame synchronizing apparatus for SMPTE 260M signals is constructed by conventional techniques, the power consumption is increased when the frame synchronization is detected from the serial data, and the time consumption is increased when the frame synchronization is detected from the parallel data and any bit-shift error to be corrected occurs. Moreover, if the time required for the bit-shift error correction is attempted to be shortened, there arises a problem in that the circuit scale for detecting bit-shift errors is greatly increased.